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Verilog::CodeGen
Verilog::CodeGen module is a Verilog code generator....
Verilog-Perl
Verilog-Perl offers an overview of Verilog language packages for Perl....
Verilog::SigParser
Verilog::SigParser is a Perl module for signal parsing for Verilog language files....
Verilog::Parser
Easily parse Verilog language files...
Verilog::Pli::Net
Verilog::Pli::Net is a Verilog PLI tied net access hash....
Text::EP3::Verilog
Text::EP3::Verilog Perl module contains a verilog extension for the EP3 preprocessor....
Python module extension Verilog verilog extension EP3 preprocessor
Verilog::Netlist::Net
Verilog::Netlist::Net is a Net for a Verilog Module....
Hardware::Verilog::Parser
A complete grammar for parsing Verilog code using Perl...
SimShop
Easy Verilog simulation...
simulation simulator Verilog simulation environment Verilog simulator
Covered
Covered is a Verilog code coverage analysis tool....
systemverilog
systemverilog is a Vim plugin that offers syntax highlighting for SystemVerilog....
HDLmaker
HDLmaker is a Verilog/VHDL code generator and FPGA development system....
SVEditor
A SystemVerilog Editor for Eclipse...